Design Engineer – Physical II

About the RoleThe Design Engineer – Physical II will be responsible for physical verification and signoff activities for complex semiconductor designs. The role involves ensuring that layouts meet foundry requirements, design rules, and signoff criteria prior to tape-out. The engineer will collaborate with physical design, layout, and technology teams to ensure robust verification flows and resolve layout issues efficiently.Key ResponsibilitiesPhysical Verification & SignoffPerform physical verification including DRC, LVS, ERC, and DFM checks using industry-standard verification tools.Execute signoff verification flows for complex designs across hierarchical and flat methodologies.Analyze verification results and work closely with layout and design teams to resolve violations.Layout ValidationValidate layout compliance with foundry rules and process requirements.Ensure adherence to design rule checks and manufacturability constraints before tape-out.Parasitic ExtractionExecute parasitic extraction (PEX) and validate extraction results for accuracy and completeness.Support timing and signal integrity teams with extracted data for analysis.Automation & Flow DevelopmentDevelop and maintain automation scripts using Tcl, Python, or Perl to streamline physical verification flows.Improve verification runsets, automation frameworks, and regression flows.Technology & Design EnablementWork with design enablement kits, technology files, and runsets provided by foundries.Contribute to verification methodology improvements and documentation.Cross-Functional CollaborationWork with physical design, layout, timing, and signoff teams to resolve design issues.Participate in debugging complex layout problems and providing verification support during tape-out.Required Skills & ExperiencePhysical Verification ExpertiseStrong hands-on experience in physical verification and signoff flows for advanced semiconductor nodes.Verification ToolsCalibre (DRC / LVS / ERC / DFM)ICV (IC Validator)Pegasus (optional but beneficial)Methodology KnowledgeStrong understanding of foundry design rules and signoff requirementsKnowledge of hierarchical and flat verification strategiesExperience with parasitic extraction (PEX) and extraction methodologiesFamiliarity with design enablement kits and runsetsScripting & AutomationProficiency in Tcl, Python, or Perl for flow automation and verification improvements Soft SkillsStrong analytical and debugging skillsAbility to work across cross-functional engineering teamsGood written and verbal communication skillsAbility to work within tight project timelines and tape-out schedulesEducationM.Tech / MS / B.Tech in Electronics, VLSI, Microelectronics, or related discipline

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