Job Title:
Principal Verification Design Engineer
Company: Cadence System Design and Analysis
Location: Pune, Maharashtra
Created: 2025-09-13
Job Type: Full Time
Job Description:
Job Description Design and lead high speed IP (USB3, PCIE, DPHY etc) development. Need to be a strong individual contributor in analog domain. Will be required to participate in all aspects of development – analog design, layout, digital design, documentation and silicon validation. Would be required to participate in customer facing discussions. Requirements B.Tech/BE/ME/Mtech Exp - 5 +yrs • Hands on design experience in various analog IP like PLLs, data converters, serial interfaces etc. • Must have participated in full cycles of analog IP creation – right from spec to silicon debug and char • Must have good communication skills and should be team player. • Working experience in PHY (PCIE, USB2, USB3) development is desired