Principal Static Timing Analysis (STA) Engineer – SoC Design

Faststream is hiring a Seasoned STA Engineer. Here are some details on what is expected.Responsibilities:Lead timing closure for sub-system/partition or full-chip level designsCollaborate with RTL, DFT, and IP teams to drive iterative timing feedback and closureDeliver timing collateral and signoff reports per project milestonesPerform timing correlation between PD tools and signoff tools; support early feasibility studiesGenerate and push down ECOs to block-level teamsMentor junior engineers and provide technical leadership across teamsDevelop automation scripts in Perl, Python, and TCL to improve timing workflowsManage timing constraints compatible with synthesis, P&R, and STA toolsQualifications:Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 8+ years of related professional experienceProven success in timing analysis and closure across multiple ASICs/SoCsExperience with advanced timing concepts: SI, CDC, LVF, POCV, etc.Proficiency in STA tools (e.g., Synopsys PrimeTime), scripting, and UNIX environmentsStrong communication skills and ability to work independently and collaborativelyExperience leading timing closure efforts across teams preferredFamiliarity with timing methodology and flow development preferred

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