Sr. ASIC Design Verification Engineer – TB Architecture

Hi - We are looking for a senior ASIC Design Verification engineer who owns testbench architecture, not just tests. This role is about building scalable UVM environments and driving SoC verification from spec to silicon.Experience: 8+ years (ASIC only)Location BangaloreWhat you will doArchitect and build scalable UVM testbenches from scratch at subsystem and SoC levelOwn testbench architecture: structure, reuse, scalability, maintainabilityDefine verification strategy and test plans from specs and micro-architectureDevelop tests, scoreboards, checkers, SVA, and coverage modelsDrive functional, code, and assertion coverage closureLead SoC-level verification: IP integration, coherency, low power, resets/bootDebug complex issues and support pre/post-silicon correlationWhat we need8+ years of hands-on ASIC verification (FPGA/emulation-only doesn’t count)Strong ownership of TB architecture, not just test writingMultiple production ASIC tapeouts (SoC or large subsystems)Expert in SystemVerilog, UVM, SVAExperience with AXI/ACE, DDR, PCIe, coherency, memory fabricsProven strength in test planning, closure, and deep debugCheers,Shahid

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