Memory Design Engineer-SRAM

Job Description: The person should have  hands on  experience(>8 Yrs.) on  full custom Memory design & architectures, Characterization , Layout design, net-listers, complete SRAM Design verification  at compiler level (not only at instance level) covering both design and layouts. The person should ensure to populate and publish  Execution plan ,  Design   Quality plan ,  DFMEA , Publish project health along with reporting of any risk and mitigation strategy. - Good knowledge on different types of Memory architecture. - Hands on experience on SRAM leafcell gds from scratch till top level integration. - Expertise in working on memory layout design for advanced nodes  (TSMC : 7nm/5nm/3nm) is must. - Proficient in various physical verification flow debug, like DRC, LVS, DFM, PERC, ERC, EM, IR.. - Proficient in Cadence virtuoso layout editor and caliber Physical verification flow. - Synopsys Custom compiler experience is huge plus. - Understanding and working knowledge of good layout practices in lower process nodes like 7nm and 5nm. - Expertise working on FinFET architecture and challenges such as variability and manufacturability - Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustness - Expertise in performing debugging of silicon failures and identify layout-related issues - Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler -Experience required 8+ years share resume on

Apply Now