Quantum Error Correction Engineer (Hardware-Aware)

Role summary We are building a system that implements surface-code quantum error correction with a hardware-accelerated pipeline (multi-FPGA). We already have the FPGA architecture expertise in-house . This role is for a surface-code implementation specialist , someone who understands the surface code deeply and has practical experience with decoder implementations / syndrome-processing pipelines . You will be the person who makes the surface code “real” at the implementation level: clear algorithmic choices, concrete dataflows, executable reference models, and unambiguous specs that our FPGA team can implement and verify. What you’ll do Own the surface-code implementation plan (algorithm → implementation) Define the full syndrome processing + decoding workflow for the chosen surface-code setup Identify performance targets: cycle-level latency constraints, throughput requirements, scaling behavior Decoder strategy + practical implementation details Evaluate or define a decoder approach suitable for real-time/streaming constraints Provide implementation-ready descriptions (data structures, update rules, scheduling, approximations) Work with the FPGA architect on what belongs in FPGA vs host/control software Create implementation artifacts the FPGA team can execute Detailed algorithm spec (state machines, message formats, boundary conditions, corner cases) Reference implementation in Python/C++ (or similar) to generate expected outputs Test vectors + golden models for verification (including fault/noise model assumptions) Support integration + validation Debug mismatches between reference model and hardware behavior Define success metrics (logical error rate targets, latency budget, resource scaling) Must-have qualifications (non-negotiable) Deep working knowledge of surface code QEC beyond textbook level (stabilizers, syndrome extraction, decoding, boundaries/defects or lattice surgery—depending on your approach) Hands-on implementation experience with at least one of: Surface-code decoder implementation (research prototype or product) Real-time syndrome processing pipeline Hardware-aware acceleration work (FPGA/GPU/ASIC) for decoding or related graph problems Strong engineering skills in Python and/or C++ for reference models, test generation, and performance experiments Ability to write precise implementation specs that a hardware team can execute without ambiguity Nice-to-have (strong plus) Familiarity with practical decoder families (examples: MWPM-style , union-find , belief propagation / weighted BP , or other practical variants) Comfort with hardware constraints: streaming dataflows, fixed-point reasoning, memory locality, pipeline scheduling Prior collaboration with FPGA/ASIC teams, including verification and bring-up realities Open-source contributions, publications, or prior work demonstrating surface-code implementation What success looks like A clear decoder/workflow choice with documented tradeoffs A validated reference model + test harness that produces golden outputs A complete “implementation map” for FPGA: inputs/outputs, message formats, timing assumptions, corner cases Smooth integration with our multi-FPGA system and measurable performance progress How to apply Send to : Resume/LinkedIn profile A short description of your most relevant surface code implementation work Links to any code, papers, talks, or projects (optional but highly valuable)

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