SENIOR RTL / FPGA DESIGN ENGINEER - AVIONICS

About UsJoin a team that is redefining the accessibility of space. Azista Space is a transformative force in the global aerospace sector, uniquely positioned at the intersection of indigenous innovation and industrial scalability. Operating India’s first private-sector satellite mass-production facility in Ahmedabad, we have bridged the gap between complex engineering and high-volume manufacturing.As a vertically integrated leader, we provide end-to-end solutions from the precision design of satellite buses and advanced payloads to mission management and communication systems. We don’t just build hardware, we are democratizing the final frontier by providing global clientele with the cost-effective, high-performance technology needed to power the next generation of orbital missions. At Azista, you won't just be starting a job, you’ll be fueling the future of space exploration.Role Summary:We are seeking a Senior RTL/FPGA Design Engineer to design, develop, and validate FPGA-based digital hardware for satellite Ground systems (ATE's, Simulators & Emulators). The role involves end-to-end ownership of FPGA development from system and micro-architecture through RTL implementation, verification, hardware bring-up, and system level validation working closely with system, hardware, PCB, and embedded software teams to deliver reliable, high-performance and optimised designs.Responsibilities:Decode the onboard design & specifications and develop a optimised ground support hardware, which includes customised ATE's, Simulators & Emulators for various satellite sub-systemsContribute to system, DSP, and board-level architecture for satellite sub-systemsPartition algorithms across FPGA hardware and embedded softwareDesign and develop RTL using VHDL / Verilog for datapaths, control logic, and interfacesCreate micro-architecture specifications, block diagrams, and design documentationPerform functional simulation, timing analysis, create FPGA constraints (XDC/SDC files) and achieve timing closureSynthesize and implement designs using Xilinx Vivado & Microchip Libero and integrate IP coresSupport board-level bring-up, debugging, and lab validation using JTAG, logic analyzers, and oscilloscopesCollaborate with PCB, systems, and embedded teams on interfaces, pinout, and constraintsSupport subsystem integration and troubleshooting at test facilitiesPrepare and maintain SRS, test plans, ATPs, validation and compliance documentationParticipate in design reviews and readiness reviews following aerospace-quality processesEducation & Experience:B.E./B.Tech in Electronics & Communication / Electrical / VLSI (or equivalent)3 to 6 years of hands-on experience in RTL and FPGA designTechnical Skills (Must-Have)Strong experience in VHDL RTL design (working knowledge of Verilog)Hands-on with Xilinx FPGA toolchain (Vivado) – synthesis, P&R, constraints, timing closureFunctional and timing simulation; testbench developmentBoard-level debugging and lab validation experienceSkilled in timing constraints (SDC/XDC files) and Static Timing Analysis (STA)Interfaces: PCIe, Ethernet, UART, SPI, I²CFamiliarity with DDR / LPDDR memory interfaces and AXI protocolsVersion control using Git / SVNTools & Technologies:HDLs: VHDL, Verilog (SystemVerilog / SystemC – plus)FPGA Tools: Xilinx Vivado; timing and simulation toolsLab Tools: JTAG, logic analyzer, oscilloscopeModeling: MATLAB / OctaveVersion Control: Git (SVN acceptable)Nice-to-Have / Domain Skills:Experience with satellite, aerospace, defence, or safety-critical systemsDSP implementation on FPGA (FFT, FIR, fixed-point optimization)Knowledge of fault-tolerant and radiation-mitigation techniques (ECC, SEU, TMR)Strong documentation and cross-functional communication skills

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