Design Engineer

Job Title: Senior Staff RTL Design Engineer We are seeking a highly experienced Senior Staff RTL Design Engineer to join our SoC development team. This role involves RTL design for chiplet based power efficient chips and collaborating across architecture, verification, and physical design teams to deliver world-class semiconductor solutions. Job Summary Design and implement RTL for IPs and chip level using Verilog/SystemVerilog and industry-standard methodologies Optimize RTL for timing, power, and area targets while ensuring design scalability Work closely with architecture, firmware, and physical design teams during development and implementation Collaborate with verification teams to ensure functional correctness and coverage goals Work closely with synthesis and physical design teams for PPA analysis and convergence Work with DFT teams to achieve coverage goals Contribute to methodology improvements for design implementation and timing closure Provide technical leadership and guidance to junior engineers Provide support to functional validation teams in post silicon debugQualifications BTech/MTech in Electrical/Electronic Engineering, Computer Engineering or Computer Science with hardware engineering experience of 8+ years in IP/chip-level RTL design Experience in D2D protocols like UCIe or Bunch-of-wires Proven track record in timing closure and physically aware design flows Strong communication skills (written and verbal), problem solving, teamwork, attention to detail, commitment to task, and quality focus Strong understanding of synthesis, STA, and power optimization techniques Experience with low-power design techniques and multi-clock domain architectures Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers Domain knowledge of clocking, system modes, power management, debug, security is a plus

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