Design Verification Engineer

Proxelera stands at the forefront of outsourced product development, specializing in advanced Semiconductor, System, and Custom Hardware engineering. With rigorous methodologies and cutting-edge expertise, we deliver next-generation solutions and cultivate a strong VLSI talent ecosystemAbout the job:Proxelera is hiring Senior Design Verification Engineers skilled in SOC/Subsystem level verification, UVM methodology, advanced testbench creation, and verification of complex semiconductor designs. Grow with us and work on cutting-edge silicon.Minimum Qualifications required:- 5+Yrs of Experience in Verification - Own UVM-based constrained-random verification for complex SoC/IP subsystems. - Develop testbenches, sequences, scoreboards, and checkers; close coverage (FC/CC/SC). - Must have SystemVerilog/UVM, assertions (SVA), functional coverage, and regressions. - Experience with bus protocols (AXI/AHB/APB/PCIe), cache/Coherency, and interrupts. - Debug with waveforms, CDC/RDC awareness, lint, and formal/property checks. - Tools: VCS/Questa/Xcelium, Verdi/DVE, Jenkins/CI, code reviews. - Strong scripting (Python/Perl/TCL), Make/CMake, version control (Git). - Work with architects/design/DFT/PD for spec clarification

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