Technical Lead - STA

Hiring: Technical Lead - STA Location:Hyderabad / Bangalore ⏳Experience:10+ Years Notice Period:Immediate to 30 Days PreferredRole Overview We are looking for an experiencedStatic Timing Analysis (STA) Engineerwith strong expertise in timing sign-off for complex SoC designs. The candidate should have hands-on experience in timing closure, constraints development, and working closely with PD and RTL teams to achieve design closure.Key Responsibilities Performblock and full-chip Static Timing Analysisfor complex SoC designs Develop and validatetiming constraints (SDC) Drivetiming closureacross different corners and modes Analyze and debugsetup/hold violations Work closely withPhysical Design, RTL, and Architecture teams SupportECO implementationfor timing fixes Handletiming sign-offfor tape-out Performclock tree and timing path analysisMandatory Skills Strong expertise inStatic Timing Analysis (STA) Hands-on experience withSynopsys PrimeTime Strong understanding oftiming constraints (SDC) Experience intiming closure and sign-off Understanding ofclocking architecture and CDC concepts Exposure toadvanced technology nodes Good understanding ofPhysical Design flowGood to Have Experience withCPU/GPU or high-performance SoC designs Knowledge ofLow Power (UPF/CPF) Exposure toSynthesis and PD flow Experience inECO and sign-off flowsRequired Experience 10+ years of experience in STA / Timing Analysis Strong debugging and problem-solving skills Ability to work independently and drive timing closureInterested candidates can share resumes withvinay.kaki@

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