Physical Design Planning/Backend Integration

Role : Sr Physical Design Lead/Backend IntegrationThis position is for senior level engineer Full Chip Physical Design/Integrations/ SoC Floor planning/Bump Planning/ Pin Assignments /Feed through/ LFU Optimization/Physical Verification, Power design/implementation/signoff. He must have hands on Physical Design experience and must have handled RTL to GDS II at Top levelKey Responsibilities:- Expertise in hierarchical RTL2GDSII design implementation - Expertise in pin assignment, Power planning, IO/Bump Planning, Pad Ring Creation, Die File Creation, RDL Routing, working with Package Team for Optimize the Bumps - Full chip Hierarchical Floor Planning, Block planning , block level constraints, hierarchical clock tree implementation, block integration and chip finishing for Analog-Mixed Signals. - Experience in debugging LVS issues at chip-level with complex analog-mixed signal IPs - Low power design with power estimation/optimization including clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption. - excellent debugging skills - Expertise in FC (Fusion Compiler) - Expertise in Primetime, Calibre for DRC/LVS, Ansys Redhawk EMIR - Soft Skills – - Should be able to drive decision with cross functional Teams. - Good Communication SkillsAcademic CredentialsBachelors or Master's degree in Computer/Electronics/Electrical Engineering

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