Senior RTL Design & Verification Engineer

We are seeking an experienced, highly motivated and high-caliber individual with below expertise. Does this sound like a good role for you?- Staff RTL Design & Verification Engineer (SOC/Subsystem level) - Location: Bangalore - Experience: 5yrs to 12yrs - BSEE/MSEE in Electrical Engineering, Computer Engineering, or a related field. - 5 years of hands-on experience in RTL design and verification (SOC/Subsystem). - Proficiency in Verilog, System Verilog, TCL scripting, and Formal Verification methodologies. - Experience working in Unix/Linux environments. - Strong debugging and problem-solving skills, especially in complex chip design environments. - Excellent written and verbal communication skills in English. - Knowledge of digital, analog, and mixed-signal IP/circuit design (a plus). - Familiarity with 3D-IC standards and semiconductor verification best practices (desirable). - Responsibilities: - Designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects. - Developing comprehensive test cases to ensure robust product functionality and performance. - Collaborating with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis. - Staying current with emerging trends, standards, and best practices in SLM and 3D-IC technologies. - Contributing to the improvement of verification methodologies and automation flows. - Documenting design specifications, verification plans, and results to ensure transparency and repeatability. - Participating in code reviews and technical discussions to drive innovation and continuous improvement.Please share your updated CV with taufiq@ or refer those who would like to explore this opportunity.- Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.

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