Design Verification Lead / Engineer

This role will oversee architecture of a verification environment from scratch. The role involves creating test plans and implementing a top-down DV flow in collaboration with the design and architecture teams, implementing robust and re-usable DV environments for deployment across various classes of devices. Responsibilities: 1. Responsible for architecting DV methodology, flow development, test plan creation and execution 2. Perform chip verification in cooperation with design, architecture, system validation and software teams 3. Responsible for DV testing plans: propose appropriate DV strategies, build test platforms, develop test cases and ensure the quality of verification with coverage tools Criteria / Requirements · In-depth DV experience of at least 10 years in building a test environment from scratch is a must. This involves understanding specifications, creating a comprehensive test plan, architecting a top level testbench and associated environment and leading all the way to coverage closure. · Expertise with verification tools (e.g. Verilog, system Verilog, UVM, OVM, etc.) · Experience in standards-based verification like MIPI, USB3, Ethernet is preferred. · Experience in DV of power-aware designs preferred. · Should be a self-starter and be able to come up with a verification strategy for new devices that do not have a legacy device as a reference. · Person should be 100% hands-on and motivated to contribute individually towards exciting opportunities to build industry-first products.

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