Opportunity With Tessolve Semiconductor- Bangalore Hi All, we are hiring RTL design engineer and design verification engineer for Bangalore location. Exp: 5+ yr exp Skills: RTL ASIC, CDC, Lint, Synthesis, Spyglass We are hiring for RTL ASIC engineer work experience in ASIC/IP Design. Experience in Logic design / RTL design Experience is IP design and integration. Experience in using the tools in ASIC development such as Lint and CDC are a must. Experience in Synthesis / Understanding of timing concepts is a plus. Good to have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Interested candidates, Kindly share updated cv to or connect on Regards, Gayatri Kushe )