Design and Verification

Greetings from ACL Digital! We are expanding our Design & Verification teams and looking for skilled professionals across multiple DV roles.Interested candidates can apply or refer friends by sharing resumes to prabhu.p@ — referrals are most welcome.JD 1 – Formal Verification Engineer• 4–13 years of Formal Verification experience• IP & SoC-level formal verification exposure• Low-speed peripherals: I2C, SPI, UART, GPIO• Strong in properties, assertions & proofsLocation: Bangalore | NP: 30 DaysJD 2 – Principal / Lead Design Verification Engineer• 15+ years of DV experience in IP & SoC verification• Strong Verilog, SystemVerilog & UVM expertise• Own end-to-end DV: test planning, execution, debug & sign-off• Lead and mentor senior DV teamsLocation: Bangalore | NP: 30 DaysJD 3 – Senior Design Verification Engineer (Cloud / Google)• 8+ years of DV experience• Strong IP & SoC verification using SV/UVM• Excellent debug, coverage and regression ownership• Hands-on experience with VerilogLocation: Bangalore | NP: 30 DaysJD 4 – Pre-Silicon / Firmware Verification Engineer• 5–12 years of pre-silicon verification experience• Boot code & firmware verification using SoC C-based flows• SV/UVM for functional or mixed-signal DV• Protocols: SPI, I2C, CSI2, LVDS, CPU verificationLocation: Bangalore | NP: 30 DaysJD 5 – AMS Verification Lead• 12+ years of AMS verification experience• Ground-up AMS SV/UVM environment development• SerDes experience: PCIe / USB3 / MIPI• Lead AMS DV from test planning to sign-offLocation: Bangalore | NP: 30 DaysJD 6 – SoC Design Verification Engineer• 5+ years of Design Verification experience• Strong SoC-level verification exposure• C language mandatory for SoC verification• SV & UVM experience requiredLocation: Bangalore | NP: 30 DaysJD 7 – Senior DV Engineer – Low Power• 8–10 years of DV experience• IP, Subsystem & SoC verification expertise• Strong UPF-based low-power verification• Excellent trace, debug & regression skillsLocation: Bangalore | NP: 30 DaysJD 8 – DV Engineer – Power Aware Verification• 8–12 years of DV experience• SV/UVM-based verification mandatory• UPF-based low-power & power-aware simulations• Trace and debug experience at IP/SS/SoC levelLocation: Bangalore | NP: 30 DaysJD 9 – DV Engineer – Specman• 8–15 years of Design Verification experience• Strong SV/UVM-based verification• Specman/e experience is mandatory• Mixed-language testbench exposure preferredLocation: Bangalore | NP: 30 DaysJD 10 – Processor SoC DV Lead & EngineersLead: 15+ years | Engineers: 3–10 years• Processor-based SoC verification experience• ARM Cortex-M/A, AMBA (AXI/AHB) expertise• C/Assembly testcase development• Lead to manage 10+ DV engineersLocation: Bangalore | NP: 30 Days

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