Principal DV

About the CompanyDefine and own verification strategy and methodology (UVM/SystemVerilog) at IP, subsystem, and SoC levels.About the RoleThoroughly understand and interpret Ethernet and related protocol specifications (IEEE standards, architecture specs, and micro-architecture documents) and translate them into comprehensive verification plans, assertions, and test scenarios.ResponsibilitiesArchitect scalable verification environments, reusable VIPs, and checkers.Drive coverage-driven verification, including functional, code, and assertion coverage.Lead verification planning, testbench architecture, and test plan sign-off.Identify, Review and guide complex test scenarios and corner cases. Execution & QualityEnsure first-pass silicon success through rigorous functional and protocol compliance verification.Drive bug triage, root-cause analysis, and closure across IP, Subsystem and SoC levels.Define and track verification metrics, quality KPIs, and sign-off criteria.Validate performance, stress, and corner scenarios such as congestion, backpressure, and error injection.Support emulation, FPGA prototyping, and post-silicon validation for Ethernet bring-up and debug. Cross-Functional CollaborationWork closely with architecture, RTL, DFT, physical design, firmware, and software teams.Provide early verification input during architecture and micro-architecture definition, especially around standards compliance and performance assumptions.Collaborate with software teams on driver, firmware, and traffic validation. Mentorship & ProcessMentor and technically guide verification engineers across experience levels.Establish and enforce verification best practices and coding standards.Drive continuous improvements in verification flows, reuse, and productivity. QualificationsBachelor’s or Master’s degree in Electrical/Electronics Engineering or related field from reputed college.10+ years of experience in ASIC/SoC design verification. Required SkillsStrong hands-on expertise in SystemVerilog, UVM, and SVAStrong understanding of Ethernet architecture and protocols (MAC, PCS, PHY interfaces). Preferred SkillsNone specified. Pay range and compensation packageNot specified.Equal Opportunity StatementWe are committed to diversity and inclusivity.

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