Lead DesignVerification UCIe PHY IP Engineer

Lead DesignVerification (DV) execution of UCIe PHY IP.Drive internal DV team meeting for day to day execution. Work closely with RTL, AMS system modelling and PD teams.Lead technical alignment on verification strategies. Define and architect verification environments and methodologies.Take initiative to drive overall execution efficiency and quality improvements.Improve and evolve existing verification methodologies : Co-Simulation (Co-SIM), UPF Power Aware Simulations (UPF PA Sim), VIP/DIP integration and Verification, increase Formal Verification usage especially FPV, Safety VerificationAnalyze execution and quality issues to define, develop, and deploy new functional verification methodologies for continuous improvement.Required Qualifications:Solid background in functional verification fundamentals.Experience in:Verification environment developmentTest plan creationVerification closureRTL and GLS debug skills, formal verification, PA simulationStrong SystemVerilog and UVM methodology expertise.Prior digital verification experience in serial bus multiprotocol PHY IPs (UCIE or SerDes IPs is preferred)B.E/B.Tech/M.E/M.Tech with 5+ years of experience

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