Lead STA Design Engineer

Job Title: STA (Static Timing Analysis) EngineerCompany: ACL Digital Locations: Bengaluru & Hyderabad Experience: 8+ Years Industry: Semiconductor / VLSI DesignJob Summary:ACL Digital is hiring an experienced STA Engineer with strong expertise in timing analysis and signoff for complex SoCs. The ideal candidate should have hands-on experience with industry-standard timing tools like Cadence Tempus and Synopsys PrimeTime, and a deep understanding of timing closure methodologies.Key Responsibilities:Perform block-level and full-chip STA across all PVT corners and modesDrive timing closure for setup, hold, recovery, and removal checksWork extensively with:Cadence TempusSynopsys PrimeTimeAnalyze and debug timing violations and provide ECO solutionsHandle constraints development and validation (SDC)Perform clock path analysis including skew, latency, and uncertaintyWork closely with Physical Design, RTL, and DFT teams for timing convergenceSupport signoff activities including SI, noise, and variation analysisRequired Skills:Strong expertise in Static Timing Analysis (STA) methodologiesHands-on experience with:Cadence TempusSynopsys PrimeTimeDeep understanding of:Timing constraints (SDC)Multi-mode multi-corner (MMMC) analysisOCV/AOCV/POCV conceptsExperience in timing closure at block and full-chip levelKnowledge of low-power intent (UPF/CPF is a plus)Scripting skills (TCL, Perl, or Python)

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