Senior Principal Signal Integrity engineer

About the CompanyCadence Bangalore is Hiring for Senior Principal Signal Integrity engineer.About the RoleThis is a unique opportunity to join the HPP IP R&D Group at Cadence Design Systems. We are looking for a Sr Principal SI/PI Engineer who will be a key contributor to our advanced high speed IP products. This is a hands-on technical position.ResponsibilitiesWork on test chip package design SI/PI optimization and verification.Work on evaluation board design optimization for best SI/PI performance.Provide extracted and measured channel models for chip designers in the R&D team.Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries.Review customer package and board designs and simulation results.Help with providing feedback to customers to ensure best possible performance of our IP in their ASIC.Work on link performance simulations using S-parameter channel models and IBIS-AMI behavioral models.Help with SI/PI related debug of test chips or customer ASICs in the lab. QualificationsM.S. or Ph.D. Electrical Engineering (or similar degree)10+ years of experience preferably working with high speed SerDes and PHYs Required SkillsGood understanding of high speed SerDes architectureHands on lab experience with instruments like high speed oscilloscopes, TDRs, VNAs, spectrum analyzers, etc.Fluent with using 3D and 2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwaveExperience with IBIS-AMI model simulationsExperience with simulation result to lab measurement correlationGood understanding of PCB and FCBGA design rules and requirementsStrong debugging and problem-solving skillsExcellent communication and presentation skills to effectively communicate with both customers and internal stakeholders Preferred SkillsNone specified Pay range and compensation packageNot specifiedEqual Opportunity StatementCadence Design Systems is committed to diversity and inclusivity.

Apply Now