STA Engineer

STA EngineerKEY RESPONSIBILITIES: Responsible for Multi Voltage domain STA environment setup, execution and timing closure of GPUDrive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checksEnsuring timing correlation between PnR STA and timely feedbacks to PD teamGenerating block level HS session and using Top context from SoC for Block-SoC Interface timing closure.Generating timing ECO using Tweaker/PrimeClosure. PREFERRED EXPERIENCE:3+ years of experience in timing closure of high frequency blocks like CPU/GPU (> GHz range)Analyzing the timing reports and identifying both design and constraints related issues.Worked on blocks with multiple power and voltage domainsPreferred EDA tool experience: Primetime, Tweaker/PrimeClosure, InnovusStrong Understanding of DFT modes requirements for timing signoffGood understanding of physical design flow and ECO implementationStrong understanding of SDC constraints, OCV,AOCV,POCV analysisStrong TCL/scripting knowledge is mandatory. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electrical Engineering

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