RTL Design Engineer – ASIC / SoC

Hi We are hiring a hands-on ASIC RTL engineer with strong RTL coding skills who owns micro-architecture and RTL development from spec to silicon. This role is about writing real RTL that goes into production chips.What you’ll doDefine and own micro-architectureWrite, review, and own high-quality synthesizable RTL code in SystemVerilog / VerilogBuild and integrate SoC or large subsystem blocksDrive timing, power, and area closure with physical design teamsLead design reviews, debug issues, and support silicon bring-up and post-silicon validationWork closely with DV on test plans, assertions, and coverageFPGA/emulation may be used only as a secondary validation aidWhat we’re looking for8+ years of hands-on ASIC RTL coding experience (FPGA experience does not count toward this requirement)Multiple production ASIC tapeouts with clear ownershipStrong RTL coding and micro-architecture ownership (non-negotiable)Solid understanding of clock/reset design and low-power techniques (UPF, retention, isolation)Experience with AMBA protocols: AXI, ACE, AHB, APBProven collaboration with synthesis, PnR, DFT, ECO, and timing-closure teamsDirect silicon bring-up experience for owned blocksGood to haveExposure to coherency, cache/memory subsystems, DDR, PCIe, security or crypto blocksSVA for design-level assertionsTcl/Python scripting to improve RTL productivityWhat won’t be consideredFPGA-only or FPGA-heavy rolesLint/CDC-only, integration-only, or tool-running profilesPure management or architect-only roles without recent hands-on RTL workCheers, Shahid

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