Senior/Lead STA engineer

We’re Hiring: STA Engineer | 5–15 Years Experience | BangaloreCompany: ACL Digital CompanyLocation: BangaloreExperience: 5 to 15 YearsJob Type: Full-TimeACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs.If you’re an STA expert who thrives in fast-paced, technically challenging environments, we want to hear from you!Responsibilities:• Own and drive timing closure for complex SoC and ASIC designs across multiple technology nodes• Perform full-chip and block-level timing analysis using industry-standard tools (Primetime, Tempus, etc.)• Collaborate with RTL, synthesis, physical design, and verification teams to resolve timing violations• Develop and maintain timing constraints (SDC), run STA checks (setup, hold, DRV, SI), and support ECO timing closure• Contribute to methodology improvements and timing signoff strategies• Report timing status, risks, and closure plans to technical leads and project stakeholdersRequired Skills & Experience:• 5–15 years of solid hands-on experience in STA and timing closure• Strong expertise in timing concepts, constraints development, and signoff methodology• Proficient in tools like Synopsys Primetime, Cadence Tempus• Solid understanding of clock tree design, DFT, multi-mode multi-corner (MMMC) analysis• Good scripting skills (TCL/Perl/Python) to automate and debug flows• Experience with advanced nodes (7nm/5nm/FinFET) is a plus• Strong analytical, problem-solving, and communication skillsWhy Join Wafer Space?• Be part of a high-growth, innovation-driven semiconductor company• Work on state-of-the-art technologies with leading global clients• Collaborative and empowering work culture• Competitive compensation and flexible work options• Opportunity to grow your career in a technically challenging environmentInterested?Send your resume to vaishnavi.suvarna@

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