Senior Emulation/Prototyping EngineersExperience : 4-5 yearsLocation : Bangaloreexperience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu)2. Working knowledge of System Verilog & Verilog language semantics and compilation flows3. Solid understanding on SOC architecture and AXI protocol4. Good communication skills and team collaborationInterested,please drop your updated resume to janagaradha.n@