Static Timing Analysis (STA) Lead

We are seeking an experienced STA Lead with strong expertise in ASIC timing analysis and timing closure across block and/or full‑chip designs. The role requires deep understanding of STA methodologies, constraints, ECO flows, and signoff checks, along with hands‑on experience using industry‑standard EDA tools on advanced technology nodes.Key ResponsibilitiesPerform Static Timing Analysis (STA) at block‑level and/or full‑chip level using industry‑standard toolsDevelop, analyze, and validate timing constraints (SDC) including clocks, generated clocks, IO constraints, and exceptionsDrive timing closure across synthesis, PnR, and signoff stagesAnalyze and resolve setup, hold, transition, capacitance, crosstalk, and logical DRC violationsWork closely with Physical Design, Synthesis, and Clocking teams to fix timing issues using ECO techniquesPerform signoff STA across multiple PVT corners and modes (functional, scan, low‑power, test)Review STA reports and provide actionable recommendations for design optimizationSupport ECO implementation and verification to meet timing and QoR targetsContribute to methodology improvements and automation using scripting (TCL / Perl / Shell)Required Qualifications7+ years of relevant experience in STA and timing closure rolesBachelor’s or Master’s degree in Electronics / Electrical / VLSI Engineering or related fieldStrong fundamentals of ASIC design flow and timing conceptsHands‑on experience with STA tools such as: Synopsys PrimeTime / TempusUnderstanding of ICC2 / Innovus / Fusion Compiler timing interfacesSolid experience in multi‑clock, high‑frequency SoC designsGood understanding of PnR impact on timing (CTS, routing, ECOs)Proficiency in TCL scripting for STA automation and analysis

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