Verification Lead

ASIC Verification Lead Immediate opportunity for this role ASIC Verification LeadJob Title: ASIC Verification LeadLocation: BangaloreExperience: 10+ YearsBudget: 45–50 LPA Job Summary:We are looking for an experienced ASIC Verification Lead with strong expertise in ASIC verification methodologies, UVM, and System Verilog. The ideal candidate will lead end-to-end verification activities, mentor team members, and ensure high-quality silicon delivery.Key Responsibilities:Lead ASIC verification projects from planning to tape-out.Develop and implement verification strategies and test plans.Design and build scalable UVM-based verification environments.Write and debug System Verilog test benches.Perform functional, regression, and coverage-driven verification.Collaborate closely with RTL design, architecture, and physical design teams.Analyze coverage reports and drive closure (functional & code coverage).Identify and debug design and verification issues.Mentor junior verification engineers and review their work.Drive improvements in verification methodology and processes.Required Skills:10+ years of experience in ASIC Verification.Strong expertise in System Verilog and UVM.Experience in building reusable verification components.Strong debugging and problem-solving skills.Experience in coverage-driven verification methodology.Knowledge of scripting (Perl/Python/Shell) is an added advantage.Experience in handling complex SoC/IP verification projects.Excellent communication and leadership skills.Preferred Qualifications:Experience with industry-standard simulators (VCS, Questa, etc.).Exposure to formal verification concepts is a plus.Experience in low-power verification is desirable.Please mail me only if you are really interested and if your profile matches this requirement. Mail me your profile to With Regards, Victor

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