Physical Design -Head

We are looking for a Physical Design leader who has delivered complex SoCs at advanced nodes and understands what it takes to take silicon from concept to GDS without drama. This role demands technical depth, execution maturity, and the ability to build and scale strong PD teams.The MandateDrive full-chip physical design from floorplan to tapeoutArchitect power, clocking, and floorplan strategy for high-performance SoCsLead timing closure across multi-mode, multi-corner scenariosOwn PPA convergence across advanced nodes (7nm / 5nm / 3nm preferred)Oversee physical verification and signoff (DRC, LVS, IR/EM, noise, reliability)Define and refine PD methodology, flows, and automationPartner with RTL, STA, DFT, and architecture teams to ensure physical feasibilityMentor senior engineers and build a high-output PD organizationThe Profile14+ years in ASIC Physical Design with multiple successful tapeoutsStrong expertise in ICC2 / Fusion Compiler / Innovus / PrimeTimeDeep understanding of timing, SI/PI, and high-frequency design challengesStrong scripting ability (Tcl / Python / Perl)Experience in CPU, GPU, AI, or HPC-class silicon preferredExposure to chiplet / multi-die environments is a plusThis is a silicon ownership role. Strategy plus execution.Cheers, Shahid

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