Principal Engineer – Chip Design Front End

We are looking for a highly skilled Digital Front-End Lead to drive and contribute to chip-level architecture, RTL design, and verification, while managing and mentoring a high-performing team. The ideal candidate will possess deep technical expertise and leadership capabilities, with a strong background in SoC design, RTL coding, verification planning, and project management.This role requires a proactive approach to continuous improvement and collaboration across disciplines. We are specifically seeking a Verification Leader with design exposure, capable of ensuring robust verification strategies while contributing to architectural and design decisions.* Target products are not FPGA-based.** Experience with MCU products featuring ARM cores is preferred. *Key Skills - Priority Level (1(Low) - 5(High))Chip Level Verification – 5Chip-Level Use Case UnderstandingVerification Plan Formulation, Management, and ReviewExtraction of verification items and formulation of verification program stimulus specificationsBuilding Dynamic & Static Verification EnvironmentsGate-Level Simulation with Back-Annotated DelaysManagement -5Leadership Experience, Project Planning, Collaboration with Backend and Analog TeamDFE Team ManagementDocumentationContinuous Improvement SuggestionsFunctional Safety StandardsRTL Design & Quality Verification - 4 RTL Quality ControlRTL Coding Skills (Verilog HDL/System Verilog)RTL Quality Check Execution; EDA Tools for RTL Quality ChecksArchitecture Design – 3Chip-Level System Architecture DesignBlock-level microarchitecture designConstraint Creation and Synthesis (SDC/STA) - 3Timing and synthesis constraintsSynthesis trial and STA report confirmationChip Level Assembly – 3Chip-Level Assembly Using EDA ToolsPower System Design- 3Multi-Power Domain DesignPower System Model DesignTesting, On-Board Evaluation, and Mass Production Support- 3Evaluation Flow (Actual Machine Bring-up, ATE Pattern Generation)Evaluation Specifications (test items such as SCAN, BIST, and cutout tests)Power Estimate- 2Power Analysis Using EDA Tools and Design FeedbackPower Estimation During Feasibility Stage

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