STA Engineer

An STA (Static Timing Analysis) Engineer is a critical specialist in the semiconductor design lifecycle, primarily responsible for timing sign-off and closure of high-performance Integrated Circuits (ICs) and System-on-Chips (SoCs). Their goal is to ensure the chip operates at its target frequency without functional failures.Experience: Min 4+yrs - 15+ YrsKey ResponsibilitiesTiming Closure: Perform block/full-chip analysis using MMMC, fixing setup/hold violations via ECOs.SDC & Constraints: Create, validate, and manage Synopsys Design Constraints (SDC) for all functional/test modes.Advanced Analysis: Model on-chip variation (OCV), signal integrity (crosstalk), and power impacts.Collaboration: Coordinate with Physical Design/RTL teams to optimize clock trees and floorplanning.Required Skills & QualificationsTools: Proficient in EDA tools like PrimeTime or Tempus, plus Tcl scripting.Knowledge: Strong background in CMOS, digital logic, and low-power (UPF) design.Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field.Excellent communication, documentation, and collaboration skills.

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