Job Title

Lead Design Verification EngineerExperience:10+ Years Location:BangaloreJob Description: We are looking for an experiencedDesign Verification Engineerwith strong expertise inIP/Sub-system/SoC level verificationandhigh-speed protocols . The candidate will be responsible for driving end-to-end verification activities, defining verification strategies, and leading complex verification closures.Key Responsibilities: Define and executeverification plans and methodologiesfor IP and SoC level designs. Develop scalableUVM/SystemVerilog based verification environmentsfrom scratch. Leadtestbench architecture, stimulus creation, scoreboards, assertions, and functional coverage . Driveverification closureincluding coverage analysis, regressions, and sign-off metrics. Work closely withdesign, architecture, and firmware teamsfor feature validation and debug. Handlecomplex debug at RTL, gate level, and emulation/prototyping platforms . Mentor junior engineers and contribute tomethodology improvements .Required Technical Skills: Strong hands-on experience inSystemVerilog, UVM, and SVA . Expertise inIP and SoC level verification . Experience with one or morehigh-speed protocols , such as: PCIe / CXL AMBA (AXI, AHB, APB, ACE/CHI) Ethernet USB DDR/LPDDR Experience withVIP integration and customization . Proficiency indebug using industry-standard simulators(VCS / Xcelium / Questa). Strong understanding ofcoverage-driven verification and constrained random methodology . Experience inlow-power verification (UPF/CPF)is a plus. Exposure toemulation or FPGA prototypingis an added advantage.Soft Skills: Proven ability tolead verification effortsfor complex projects. Strong problem-solving and debugging skills. Excellent communication and cross-functional collaboration.Education: BE / B.Tech / MS in Electronics / Electrical / VLSI / related field.Nice to Have: Experience inmulti-core SoC / cache coherency verification Scripting knowledge inPython/Perl/Shell/TCL Formal verification exposure