Job Title

Physical Verification EngineerExperience: 2 to 5 YearsLocation: BangaloreNotice Period: ImmediateJob DescriptionKey Responsibilities:- Perform Physical Verification checks including DRC, LVS, ERC, and Antenna checks at block and full-chip level. - Work with foundry rule decks (TSMC / Samsung / GF / Intel / UMC etc.) to ensure design sign-off compliance. - Debug and resolve layout violations by working closely with the Physical Design, Layout, and Circuit teams. - Run Parasitic Extraction (PEX) and support timing and SI closure teams for accurate model generation. - Perform DFM checks and assist with design enhancements for manufacturability. - Support tape-out preparation, validation, reports, checklists, and documentation.Required Skills & Expertise:- Strong working experience with Calibre / PVS / ICV for DRC & LVS sign-off. - Understanding of CMOS layout fundamentals, standard cells, macros, and routing architectures. - Familiarity with GDS / OASIS data formats, hierarchical layout structures, and physical design flows. - Basic knowledge of STA, IR/EM, PDN, and PnR flows is a plus. - Ability to collaborate in cross-functional teams and drive closure of PV issues.Good to Have:- Experience with advanced technology nodes (7nm / 5nm / 3nm). - Scripting in Tcl, Python, or Shell to automate verification workflows. - Exposure to Custom Layout or Analog/Mixed-signal PV environments.Education:- B.E / B.Tech / M.E / M.Tech in Electronics / VLSI / Electrical / Semiconductor or related domain.