Job Title

Lead and mentor a team of RTL design engineers across multiple SoC projects. Own the design execution from specification to RTL handoff, ensuring functionality, quality, and schedule adherence. Define and implementRTL design methodologies , coding guidelines, and best practices for consistency and reuse. Collaborate witharchitecture ,verification ,DFT , andphysical designteams to ensure clean integration and design closure. Drivetiming, power, and area optimizationin collaboration with backend and architecture teams. Review specifications, micro-architecture, and RTL implementation for completeness and quality. Manage project planning, tracking, and reporting for design deliverables and milestones. ChampionAI- and automation-driven improvementsin design quality, linting, and performance validation. Contribute to recruitment, mentoring, and capability building within the design organization. Promote a culture of technical excellence, ownership, and collaboration across teams.Requirements/Qualifications:Bachelor’s or Master’s degree inElectrical/Electronics Engineeringor related discipline. 12–15 yearsof relevant industry experience, including2–3 yearsin technical or people leadership roles. Strong hands-on experience inRTL design (Verilog/VHDL/SystemVerilog)andSoC/Subsystem development . Solid understanding ofARM CPU-based architectures ,AMBAinterconnects (AXI, AHB, APB), andPCIeprotocols. Proficiency inSynthesis, STA, and timing closure flows . Experience withlinting, CDC, DFT , andlow-power design techniques . Familiarity withC/C++modeling and design validation environments preferred. Working knowledge ofAI/ML-based design optimizationorautomation scripting(Python/TCL/Perl) is a plus. Excellent analytical, communication, and cross-functional collaboration skills. Highly self-driven, detail-oriented, and committed to design quality and schedule delivery.--