Job Title

Key skills with hand on :Design Verification, System Verilog ,SOC, SV -UVM, Testplan, Test bench, VCS, Verdi, Cadence, Simvision, jasper Experience: 5 - 25 years Work Location: Trivandrum, Bangalore, Hyderabad, Chennai, Pune Education: Engineering (excluding Mechanical/Civil) Detailed JD: • 6+ years of hands-on DV experience in SystemVerilog/UVM. • Must be able to own and drive the verification of a block / subsystem or a SOC. • Should have a track record of leading a team of engineers. • Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. • Experience in Tesplan and Testbench development, • Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. • Should be good with debugging and exposed to all aspects of verification flow including Gatesims • Must have extensive experience in verification of one or more of the following: o PCI Express or UCIe, CXL or NVMe o AXI, ACE or CHI o Ethernet, RoCE or RDMA o DDR or LPDDR or HBM o ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages o Power Aware Simulations using UPF • Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. • Experience in using one or more of revision control systems such as: Git, Perforce, Clearcase. • Experience in SVA and formal verification is desirable (not a must) • Script development using Python, Perl or TCL is desirable (not a must)