DV with Soc, DDR Exp, UVM, OVM, Verilog, System Verilog Exp: 8+yrs Loc: BLR NP: Immediate to 30 days If Interested, please share your profile to my mail id
Job Title
Design Verification Engineer DDR
Design Verification Engineer DDR
DV with Soc, DDR Exp, UVM, OVM, Verilog, System Verilog Exp: 8+yrs Loc: BLR NP: Immediate to 30 days If Interested, please share your profile to my mail id