Job Title

Experience Level : 14+ years of industry exp, with at least 3 years in team management At Mediatek Bangalore, we are building teams that cater to the verification challenges of our next gen Smartphone, Compute, Automotive & Data Center chips. To help strengthen our verification capabilities, we are seeking an experienced Design Verification Manger who would lead our team of highly talented engineers. The candidate should have prior experience in technical leadership - leading and managing teams towards delivery of one or more complex modules or SoC at product-based organizations. The candidate needs to have a hands-on experience with SV, UVM with proven ability to build and enhance test benches. Should have exposure to different verification methodologies and flows at IP, Sub System or SoC Level. Power Aware verification exposure, GLS verification exp is a plus. Experience in working with teams across geo’s is a plus. Key Responsibilities: Lead and manage a team of highly motivated design verification engineers, providing technical guidance, mentorship and team management. Architect and develop new testbenches or enhance existing testbenches using System Verilog and UVM methodologies. Own the functional verification of RTL designs at IP/Sub System/SoC level by driving the development & implementation of comprehensive verification plans, including coverage closure and GLS, ensuring high-quality and robust designs. Collaborate closely with design, architecture, and software teams to ensure robust verification coverage and timely project delivery. Participate in design/verification planning reviews, test plan reviews, methodology reviews, providing technical expertise and insights. Define and implement best practices for verification flows and automation. Generate and analyze verification metrics to regularly track project progress, identify risks, and proactively resolve technical and resource challenges. Foster a culture of continuous improvement, innovation, and high-quality deliverables within the team. Qualifications & Experience: Bachelor's or Master's degree in Electrical/Electronics/Instrumentation/Computer Engineering, or related fields from an institute of repute. 14+ years of industry exp, with at least 3 years in team management Strong hands-on experience in TB design, test plan creation. Proficiency in verification flows, methodologies and languages such as System Verilog & UVM Track record of successfully leading and managing verification of complex IP blocks, Subsystems or SoC Modules at product-based organizations. Ability to work collaboratively in a fast-paced environment spanning across geographies. Handling stakeholders across geographies. Strong problem-solving skills and people skills are needed. Need to have excellent oral and written communication skills. Knowledge or experience in areas like on chip memory, DDR, HBM, High Speed IO’s , HDMI , PCIe is a plus